Matrix operation processing device

ABSTRACT

An input signal data string I is temporarily stored in a register, and is input to an adder according to the instruction of a control unit. The control unit designates a ROM storing a check matrix H and obtains information about a position, in which 1 is stored in a specific column of the check matrix. The ROM instructs SEL 1#1  through #CW to select a value corresponding the position, in which the check matrix is 1 from values from reg(M) using a selector SELL and sends it to an adder. If the result of an addition is selected by a selector SEL 2  instructed to select it by the ROM, then it is input to the reg(M). If no addition has been applied, the value output from the reg(M) is input to the reg (M) again through the selector SEL 2.  This process is repeated until all the operations have finished.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a matrix operation processingdevice.

[0003] 2. Description of the Related Art

[0004] Currently, many data processing devices, including personalcomputers, are commercialized and are put into practical use. In suchdata processing devices, data is stored or transferred after beingencoded. In particular, if digital signals are received from astorage/reproduction medium, such as a magnetic disk, an optical disk, amagneto-optical disk and the like, or a network, and are decoded, anLDPC (low density parity check) code is sometimes used for errorcorrection.

[0005] In order to obtain a process result P using N bits of signal datastring I and N×M bits of check matrix H, the matrix operation P=H*I^(T)is needed. For example, if the following equation holds true,$\begin{matrix}{{I = \left\lbrack {i_{0},i_{1},\Lambda,i_{N - 1}} \right\rbrack},\quad {P = \left\lbrack {p_{0},p_{1},\Lambda,p_{M - 1}} \right\rbrack},} \\{H = \begin{bmatrix}h_{00} & h_{01} & \Lambda & h_{{0N} - 1} \\M & M & M & M \\h_{M - 10} & h_{M - 11} & \Lambda & h_{M - {1M} - 1}\end{bmatrix}}\end{matrix}$

[0006] the process result P can be calculated as follows.$\begin{matrix}{P_{m} = {\sum\limits_{n = 0}^{N - 1}{h_{mn}*i_{n}}}} & (1)\end{matrix}$

[0007] In this case, for example, a magnetic disk device being a typicalstorage/reproduction medium is provided with an error correctionfunction. An LDPC code is one of possibly many codes used for such errorcorrection. In this case, calculating this code requires such a matrixoperation.

[0008] A check matrix used for a parity calculation or an LDPC decodingcontains only binary values (1s and 0s. In this case, equation (1) is asfollows. $\begin{matrix}{P_{m} = {\sum\limits_{n = {{0/h_{mn}} = 1}}^{N - 1}i_{n}}} & (2)\end{matrix}$

[0009]FIG. 1 shows a conventional matrix operation circuit.

[0010] In order to obtain the process result P by performing such aprocess, equation (2) must be calculated after the full data of thesignal data string I are obtained.

[0011] After all the full data of the signal data string I are stored ina register 40, a selector SEL 42 selects items, the value of which is 1in each row read from a ROM 14 and the like storing a matrix datum H,and an adder 46 adds the items. The result of the addition is stored ina register 43. In this case, RW represents the maximum number of 1s ineach row. By repeating this process M times, the process result P can beobtained. In this case, if the selector and adder are shared until thefull data of P are obtained, the process runs in O(N+M) time and causesgreat delay, which is a problem. In this case, a storage register N witha large circuit scale and/or RW adders is also needed.

[0012]FIG. 2 shows another conventional matrix operation circuit.

[0013] In this conventional matrix operation circuit, after the fulldata of a signal data string I are stored in a register 44, an adder 47wired based on the matrix H calculates the full data of the processresult P. The result is stored in a register 45 and is output. In thiscase, although only O(N) time is needed to obtain the full of data of P,the size of a storage register N and the circuit scale become largesince RW×M adders are needed, which is another problem.

SUMMARY OF THE INVENTION

[0014] It is an object of the present invention to provide a matrixoperation processing device performing a high-speed matrix operationwith a small circuit scale.

[0015] The matrix operation processing device of the present inventioncomprises a storage unit storing the elements of a matrix; a registerstoring a value, all initially set all 0s, and sequentially storing theresult of a sequentially performed operation; an adder adding an inputdata value to a value output from the register; an operation controlunit inputting a necessary value in the register to the adder, based onthe matrix element value and adding an input data value to the valuefrom the register; and a loop-back unit appropriately selecting theoutput of the adder and the output of the register and storing them inthe register again.

[0016] According to the present invention, the number of adders and thecircuit scale can be reduced compared to the conventional circuit. Ifonly necessary information about a matrix is stored, memory capacity canalso be reduced and a small high-speed matrix operation processingdevice can be realized.

BRIEF DESCRIPTIONS OF THE DRAWINGS

[0017]FIG. 1 shows a conventional matrix operating circuit.

[0018]FIG. 2 shows another conventional matrix operating circuit.

[0019]FIG. 3 shows an example configuration of the matrix operationcircuit according to the preferred embodiment of the present invention.

[0020]FIG. 4 shows an example circuit representing the operation of thepreferred embodiment of the present invention.

[0021]FIG. 5 shows an example of the realized control unit according tothe preferred embodiment of the present invention (No. 1).

[0022]FIG. 6 shows an example of the realized control unit according tothe preferred embodiment of the present invention (No. 2).

[0023]FIG. 7 shows an example of the realized control unit according tothe preferred embodiment of the present invention (No. 3).

[0024]FIG. 8 shows an example of the realized control unit according tothe preferred embodiment of the present invention (No. 4).

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] In the matrix operation P=H×I^(T), obtaining a process result Pusing N bits of a signal data string I and N×M bits of a check matrix H,process delay and circuit scale are reduced by performing necessaryoperations for each column of the check matrix H and accumulating theresult for each row. In particular, in a check matrix for errorcorrecting codes needed for coding, the number of the columns M of thecheck matrix is far smaller than the number of the rows N. Therefore, bycalculating a plurality of pieces of data in each column in parallel andaccumulating the result for each row, the number of adders and circuitscale can be reduced.

[0026] The matrix operation processing device comprises a storage unitstoring a process result P, such as a register or the like; a storageunit storing a check matrix H, such as a ROM or the like; a unit readingthe check matrix H and process result P when an address counter or thelike receives a signal data string I and controlling the storage; and anoperation unit, such as an adder or the like. The device obtains columndata, the input data which must be processed every time the devicereceives a signal data string I, from H, reads necessary items of atarget process result P, multiplies the received data by the necessaryitems and writes the result back into the storage unit as the processresult P. By repeating this process for all the full received data ofthe signal data string I, a process result P can be obtained.

[0027]FIG. 3 shows an example configuration of a matrix operationcircuit according to the preferred embodiment of the present invention.

[0028] A control unit 10 controls the reception of a signal data stringI and stores it in a storage unit reg 12. The control unit 10 alsoobtains the position of a target process result P in the column from astorage unit 11 for a check matrix H, based on the position of thereceived data. A storage unit reg(M) 13 for the process result P isinitialized to all 0s prior to data reception. The control unit 10 andstorage unit 11 enable a data selector SEL 1 to select the targetprocess result P and to add input data to the process result P. In thiscase, the number of adders in the column is the same as the maximumnumber CW of 1s. SEL 1 is a selector for M→CW and the number of theselectors is also CW. SEL 2 is a selector for (CW+1)→1 and the number ofthe selectors is M. The SEL 2 judges whether each result of theadditions and data read from the reg(M) 13 is process data or originaldata, and writes them back into the reg(M) 13.

[0029] Specifically, in FIG. 3, one bit of the signal data string I isstored in the reg 12, is read by the control unit 10 and is input toeach adder. The control unit 10 detects the position of an element withvalue 1 in an appropriate column of the check matrix from a ROM 11, aselector SELL corresponding to the position of the element with value 1in the column of the check matrix selects a value output from the reg(M)13, from signals output from the reg(M) 13 and adds the value to thesignal data string. The result of the addition is sent to a selectorSEL2. The selector SEL2 inputs a data value, to which addition has beenapplied in the adder, to the reg(M) 13. As for a data value to whichaddition has not been applied, the selector SEL2 inputs the value to thereg(M) 13 again. When the reception/operation of all the signal datastrings I finish, the reg(M) 13 outputs output data P.

[0030] Speaking more conceptually, it is determined to which column theelement of an input signal data string I should be multiplied when the Iis read, by obtaining the offset of the I. If an I is input, the columnto be used of a check matrix is read and the operations using parallelcolumns are performed in parallel (In reality, since the elements of acheck matrix are 0 and 1, the matrix element of which is 1, is input toan adder without performing any process). Then, the result of theoperation is stored in the reg(M), and it is added horizontally everytime an I is sequentially input. When all addition finishes, a parityrow vector is obtained and the operation terminates.

[0031] According to this device, data process running time is O(N). Asfor circuit scale, the respective number of adders and storage registersbecome CW and M, respectively.

[0032] If the storage unit for a check matrix H stores the address of aposition taking 1, (Cadd1, Cadd2, Cadd3) are stored in the first addressof a ROM(H). In this case, Cadd represents the position of the n-th 1 ina column, and if the number of 1s is less than CW, the value isdesignated as 0.

[0033] For example, if H(N=8, M=5) is as follows, $H = \begin{bmatrix}1 & 0 & 1 & 1 & 0 & 1 & 1 & 0 \\0 & 1 & 0 & 1 & 1 & 1 & 1 & 1 \\1 & 0 & 1 & 0 & 0 & 0 & 1 & 1 \\1 & 1 & 0 & 1 & 1 & 0 & 0 & 1 \\0 & 1 & 1 & 0 & 1 & 1 & 0 & 0\end{bmatrix}$

[0034] data are stored as follows. TABLE 1 address data 0 (1, 2, 4) 1(2, 4, 5) 2 (1, 3, 5) 3 (1, 2, 4) 4 (2, 4, 5) 5 (1, 2, 5) 6 (1, 2, 3) 7(2, 3, 4)

[0035] In this case, each address can be represented by three bits(0˜5<8). Therefore, if CW=3, 3×3=9 bits can be stored as one word.

[0036] If the offset of an input data string I is 0, (1, 3, 4) isoutput. Each of three SEL1 s from the left end selects the M of 1, the Mof 3 and the M of 4 from left to right. Then, each of the first, thirdand fourth SEL2 s from the left end selects a signal from each SEL1, andeach of the other SEL2 s selects a signal from M.

[0037] The respective realized control of SEL 1 and SEL 2 are shownbelow. If it is assumed that SELL is a selector for M→1 and a controlsignal represents m (integer), the SELL selects/outputs the m-th data.In this case, if every three bits from the MSB of the output from theROM can be designated as a control signal m, the control of the SELL canbe realized.

[0038] If it is assumed that SEL2 is a selector for 4(CW+M)→1 andcontrol signals select as follows,

[0039] 0→M; 1→SEL1#1; 2→SEL1#2 and 4→SEL1#CW

[0040] the control of the SEL2 can be realized by inputting the outputfrom the ROM to the data multiplexer decoder shown in Table 2 anddesignating the output of each decoder as control signals, as shown inTable 2. TABLE 2 input output data 0 0 (00000b) 1 1 (00001b) 2 2(00010b) 3 4 (00100b) 4 8 (01000b) 5 16 (10000b) 

[0041]FIG. 4 shows an example of the circuit representing the operationof the preferred embodiment of the present invention.

[0042] Control signals are output from a ROM (H) 1 and are input to eachof selectors SEL1#1 through SEL1#CW and each of multiplexer decodersDEC3-1 through 3-n. Signals obtained by decoding the control signalsfrom the ROM (H) 1 to the selection signals of a selector SEL2 areoutput from the multiplexer decoder DEC3-1 through 3-n. The SEL2 iscontrolled by signals from these multiplexer decoders DEC3-1 through3-n.

[0043] An example of how to generate a reading address for a matrix H

[0044]FIGS. 5 through 8 show examples of the realized control unitaccording to the preferred embodiment of the present invention.

[0045] First, if at the top of an input data string I, data_start is asshown in FIG. 5 and during the valid time period of the data I,data_enable is as shown in FIG. 5, a control unit can be implemented byusing a counter 22 with count enable (count up by 1) and clear (all 0 by1). In the case of the matrix described above, a three-bit counter (0˜7)can function as the control unit.

[0046] As shown in FIG. 5, an M storage register can be realized byselecting output SEL2 if data_enable is 1, and storing it in an FF 21.If it is 0, the M storage register can be realized by selecting datausing a selector 20 and storing the data in a FF 21.

[0047] In this case, data_enable can also be discontinuous, as shown inFIG. 6. If data I is input in descending order, the control unit can berealized by storing H in reverse order.

[0048] In FIG. 6, the control unit can be realized by replacing thecounter with a down-counter with a loading function and loading a valueN−1 by data_start, down-counting the data by data_enable.

[0049] If data I is input in a pre-defined order, the control unit canbe realized by storing H in that pre-defined order.

[0050] If input data I is interleaved, the control unit can be realizedby storing H in that order.

[0051] The control unit can also be realized by the configuration shownin FIG. 7. In this case, n is an interleave interval. If n=2, the inputorder of the example described above (0˜7) becomes 0, 2, 4, 6, 1, 3, 5and 7.

[0052] A REG 33 is an FF storing addresses. When data_enable is 1,selectors 31 and 32 select data in the lower parts of selectors 31 and32, respectively. A comparator 34 compares the count enable of a counter30 and input to the port in the upper parts of the selectors 31 or 32.

[0053] The operations are as follows:

[0054] 1. “0” is loaded into all REGs by data_start, and 1 is loadedinto the counter 30 by clear.

[0055] 2. A value obtained by adding n to the value of the REG 33 can beloaded (set) by data_enable.

[0056] 3. It is tested whether REG>N−1. If it holds true, the processproceeds to step 4. If it does not hold true, the flow returns step 2.

[0057] 4. The flow returns to step 1 by data_start. Otherwise, bydata_enable, a counter value is set in the REG 33. By CE, the counter 30is incremented by one and the flow returns to step 2.

[0058] If in this configuration, n=1, data in ascending order withoutinterleave are obtained.

[0059] In the configuration shown in FIG. 8, the operations are asfollows, and data interleaved and in reverse order can be obtained.

[0060] 1. N−1 is loaded into the REG 33 by data_start, and N−2 is loadedinto the counter 30 by clear.

[0061] 2. A value obtained by subtracting n from the value of the REG 33is loaded (set) by data_enable.

[0062] 3. It is tested whether REG=0. If it holds true, the flowproceeds to step 4. If it does not hold true, the flow returns to step2.

[0063] 4. The flow returns to step 1 by data_start. Otherwise, bydata_enable, a counter value is set in the REG 33. By CE, the counter 30is decremented by one, and the flow returns to step 2.

[0064] In the preferred embodiment described above, comparison is madein one example of the check matrix for LDPC codes. In this case, ifN=4352, M=256 and RW=51, in the preferred embodiment, the capacity of astorage memory becomes M/N=1/4 compared with that in the prior art. Thenumber of adders becomes CW/RW=3/51 compared with that in theconfiguration shown in FIG. 1, and becomes CW/RW×M=3/13056 compared withthat in the configuration shown in FIG. 2.

[0065] In the device of the preferred embodiment, the process isperformed for each column. Thus, the process can be performed regardlessof the order in which the N bits of a signal data string I are received.By processing data for each column, the processing of N bits of a signaldata string I can be started from an arbitrary position.

[0066] Furthermore, in the preferred embodiment, a check matrix H can bestored by storing only the address of an item to be processed.Therefore, the circuit scale of the storage unit can be reduced.

[0067] If the entire matrix is stored, capacity for M bits×N addressesis needed. However, if only its addresses are stored, only capacity forlog₂(M)bits×CW is needed.

[0068] Furthermore, by storing the order in which the signal data stringI is received using a matrix storage unit a processing device that canhandle any receiving order can be realized.

[0069] Furthermore, as described above, when a signal data string I isreceived in reverse order, there is no need to modify the circuit ifonly the addresses of the matrix are stored in reverse order.

[0070] In the device described above, by storing the order in which thesignal data string I is received using control data provided for amatrix storage unit, a processing device regardless of receiving ordercan be realized.

[0071] For example, by organizing order in which addresses are receivedinto a table using registers, dynamic modification to adapt to order inwhich data are received becomes possible.

[0072] In the preferred embodiments described above, although the numberof selectors with a fairly small circuit scale increases, the number ofadders with a fairly large circuit scale decreases. Therefore, as awhole, circuit scale can be reduced.

[0073] Since the ROM only stores the position of the is in a checkmatrix, there is no need for the ROM to store all the matrix elements.Therefore, memory capacity can be reduced. In particular, in the case ofan LDPC code, since the number of 1s is fairly small, memory capacitycan be effectively reduced.

[0074] In the description of the preferred embodiments given above,although it is assumed that the signal value of an input data string Iis a binary bit string, the present invention is not limited to this.Even when the signal value is composed of real numbers, the presentinvention is similarly applicable.

[0075] For the details of an LDPC code and its coding, see the followingreferences. Tadashi Wadayama, “Low-Density Parity Check Codes and aDecoding Method thereof”, Proceedings of the Magnetic Recording StudyGroup, December 2001,<http://vega.c.oka-pu.ac.jp/˜wadayama/welcome_j.htm 1>

[0076] (1) Tadashi Wadayama, “An Extension of Gallager Ensemble OfLow-Density Parity Check Codes”, IEICE Trans. Fundamentals, Vol.E85-A,No.1, January 2002

[0077] According to the present invention, the delay and circuit scaleof a matrix operation circuit can be reduced.

What is claimed is:
 1. A matrix operation processing device, comprising:storage unit for storing elements of a matrix; register unit for storinga value, which is initially all 0s, as an initial value and sequentiallystoring the result of a sequentially performed operation; adder unit foradding an input data value to a value output from the register unit;operation control unit for inputting a necessary value from the registerunit to the adder unit, based on an element value of the matrix andadding an input data value to the value from the register unit; andloop-back unit for appropriately selecting output of the adder unit andoutput of the register unit, and storing them back into the registerunit.
 2. The matrix operation processing device according to claim 1,wherein said storage unit only stores positions of the 1s in a checkmatrix as information.
 3. The matrix operation processing deviceaccording to claim 1, wherein said operation control unit outputsnecessary information from the storage unit in accordance with offset ofan input data value.
 4. The matrix operation processing device accordingto claim 1, wherein said matrix is a check matrix for error correctingcodes needed for data coding.
 5. The matrix operation processing deviceaccording to claim 1, wherein said matrix is a check matrix for LDPC(low-density parity check) codes.
 6. A matrix operation processingmethod, comprising: storing elements of a matrix (storage step); storinga value, initially all 0s and sequentially storing the result of asequentially performed operation in the register unit (registrationstep); adding an input data value to the value stored in the registerunit (addition step); transferring a necessary value stored in theregister unit to the adder unit, based on an element value of the matrixand adding an input data value to the stored value (operation controlstep); and appropriately selecting output of the adder unit and thestored value, and storing them in the register unit again (loop-backstep).
 7. The matrix operating processing method according to claim 6,wherein in said storage step, only positions of 1s in a check matrix arestored as information.
 8. The matrix operating processing methodaccording to claim 6, wherein in said operation processing step,necessary information is output from the storage unit in accordance withinput order of an input data value.
 9. The matrix operating processingmethod according to claim 6, wherein said matrix is a check matrix forerror correcting codes needed for data coding.
 10. The matrix operatingprocessing method according to claim 6, wherein said matrix is a checkmatrix for LDOC (low-density parity check) codes.